CMP214: COMPUTER ARCHITECTURE AND ORGANIZATION 1 (3 UNITS)
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It is difficult to give precise definition for the terms Computer Organization and Computer Architecture. But while describing computer system, we come across these terms, and in literature, computer scientists try to make a distinction between these two terms.
Computer architecture refers to set of rules and methods that describe the functionality, organisation, and implementation of the computer systems. It is also defined as the attributes of a system visible to a programmer or attributes that have a direct impact on the logical execution of a program. Examples of architectural attributes include the instruction set, the number of bits used to represent various data types (e.g., numbers, characters), I/O mechanisms, and techniques for addressing memory.
Computer organization refers to the operational units and their interconnections that realize the architectural specifications. Examples of organizational attributes include those hardware details transparent to the programmer, such as control signals; interfaces between the computer and peripherals; and the memory technology used.
For example, it is an architectural design issue whether a computer will have a multiply instruction. It is an organizational issue whether that instruction will be implemented by a special multiply unit or by a mechanism that makes repeated use of the add unit of the system. The organizational decision may be based on the anticipated frequency of use of the multiply instruction, the relative speed of the two approaches, and the cost and physical size of a special multiply unit.
INTERNAL STRUCTURE OF THE COMPUTER
There are four main structural components:
Central processing unit (CPU): Controls the operation of the computer and performs its data processing functions; often simply referred to as processor.
Main memory: Stores data.
I/O: Moves data between the computer and its external environment.
System Bus: Some mechanism that provides for communication among CPU, main memory, and I/O. A common example of system interconnection is by means of a system bus, consisting of a number of conducting wires to which all the other components attach
Fig 1: The Computer: Top-Level Structure
Figure 2 illustrates top-level components and the interactions among them. The CPU exchanges data with memory. For this purpose, it typically makes use of two internal (to the CPU) registers: a memory address register (MAR), which specifies the address in memory for the next read or write, and a memory buffer register (MBR), which contains the data to be written into memory or receives the data read from memory. Similarly, an I/O address register (I/OAR) specifies a particular I/O device. An I/O buffer (I/OBR) register is used for the exchange of data between an I/O module and the CPU.
A memory module consists of a set of locations, defined by sequentially numbered addresses. Each location contains a binary number that can be interpreted as either an instruction or data. An I/O module transfers data from external devices to CPU and memory, and vice versa. It contains internal buffers for temporarily holding these data until they can be sent on.
Fig 2: Computer Components: Top-Levels View and the Interactions among them.
COMPUTER FUNCTIONTION
The basic function performed by a computer is execution of a program, which consists of a set of instructions stored in memory. The processor does the actual work by executing instructions specified in the program. In its simplest form, instruction processing consists of two steps: The two steps are referred to as the fetch cycle and the execute cycle.
At the beginning of each instruction cycle, the processor fetches an instruction from memory. In a typical processor, a register called the program counter (PC) holds the address of the instruction to be fetched next. Unless told otherwise, the processor always increments the PC after each instruction fetch so that it will fetch the next instruction in sequence (i.e., the instruction located at the next higher memory address). In general, these actions fall into four categories:
Processor-memory: Data may be transferred from processor to memory or from memory to processor.
Processor-I/O: Data may be transferred to or from a peripheral device by transferring between the processor and an I/O module.
Data processing: The processor may perform some arithmetic or logic operation on data.
Control: An instruction may specify that the sequence of execution be altered.
For example, the processor may fetch an instruction from location 149, which specifies that the next instruction be from location 182. The processor will remember this fact by setting the program counter to 182. Thus, on the next fetch cycle, the instruction will be fetched from location 182 rather than 150.
Fig 3: Basic Instruction Cycle
COMPUTER MEMORY SYSTEM
Characteristics of Memory Systems
The complex subject of computer memory is made more manageable if we classify memory systems according to their key characteristics. The most important of these are listed in Table 1. The term location in Table 1 refers to whether memory is internal and external to the computer.
Internal memory is often equated with main memory. But there are other forms of internal memory. The processor requires its own local memory, in the form of registers. Further, the control unit portion of the processor may also require its own internal memory. Cache is another form of internal memory.
External memory consists of peripheral storage devices, such as disk and tape, that are accessible to the processor via I/O controllers. An obvious characteristic of memory is its capacity. For internal memory, this is typically expressed in terms of bytes (1 byte 8 bits) or words. Common word lengths are 8, 16, and 32 bits. External memory capacity is typically expressed in terms of bytes.
Word: The “natural” unit of organization of memory. The size of the word is typically equal to the number of bits used to represent an integer and to the instruction length. Unfortunately, there are many exceptions. For example, the CRAY C90 (an older model CRAY supercomputer) has a 64-bit word length
but uses a 46-bit integer representation. The Intel x86 architecture has a wide variety of instruction lengths, expressed as multiples of bytes, and a word size of 32 bits.
Unit of transfer: For main memory, this is the number of bits read out of or written into memory at a time. The unit of transfer need not equal a word or an addressable unit. For external memory, data are often transferred in much larger units than a word, and these are referred to as blocks.
Table 1: Key Characteristics of Computer Memory Systems
Another distinction among memory types is the method of accessing units of data. These include the following:
Sequential access: Memory is organized into units of data, called records. Access must be made in a specific linear sequence. Stored addressing information is used to separate records and assist in the retrieval process. A shared read–write mechanism is used, and this must be moved from its current location to the desired location, passing and rejecting each intermediate record. Thus, the time to access an arbitrary record is highly variable. Tape units are sequential access.
Direct access: As with sequential access, direct access involves a shared read–write mechanism. However, individual blocks or records have a unique address based on physical location. Access is accomplished by direct access to reach a general vicinity plus sequential searching, counting, or waiting to reach the final location. Again, access time is variable. Disk units are direct access.
Random access: Each addressable location in memory has a unique, physically wired-in addressing mechanism. The time to access a given location is independent of the sequence of prior accesses and is constant. Thus, any location can be selected at random and directly addressed and accessed. Main memory
and some cache systems are random access.
Associative: This is a random access type of memory that enables one to make a comparison of desired bit locations within a word for a specified match, and to do this for all words simultaneously. Thus, a word is retrieved based on a portion of its contents rather than its address. As with ordinary random-access memory, each location has its own addressing mechanism, and retrieval time is constant independent of location or prior access patterns. Cache memories may employ associative access.
Access time (latency): For random-access memory, this is the time it takes to perform a read or write operation, that is, the time from the instant that an address is presented to the memory to the instant that data have been stored or made available for use. For non-random-access memory, access time is the time it takes to position the read–write mechanism at the desired location.
Memory cycle time: This concept is primarily applied to random-access memory and consists of the access time plus any additional time required before a second access can commence. This additional time may be required for transients to die out on signal lines or to regenerate data if they are read destructively. Note that memory cycle time is concerned with the system bus, not the
processor.
Transfer rate: This is the rate at which data can be transferred into or out of a memory unit.
THE MEMORY HIERARCHY
The design constraints on a computer’s memory can be summed up by three questions:
How much?
How fast?
How expensive?
The question of how much is somewhat open ended. If the capacity is there, applications will likely be developed to use it. The question of how fast is, in a sense, easier to answer. To achieve greatest performance, the memory must be able to keep up with the processor. That is, as the processor is executing instructions, we would not want it to have to pause waiting for instructions or operands. The final question must also be considered. For a practical system, the cost of memory must be reasonable in relationship to other components.
As might be expected, there is a trade-off among the three key characteristics of memory: namely, capacity, access time, and cost. A variety of technologies are used to implement memory systems, and across this spectrum of technologies, the following relationships hold:
Faster access time, greater cost per bit
Greater capacity, smaller cost per bit
Greater capacity, slower access time
The dilemma facing the designer is clear. The designer would like to use memory technologies that provide for large-capacity memory, because the capacity is needed and the cost per bit is low. However, to meet performance requirements, the designer needs to use expensive, relatively lower-capacity memories
with short access times.
The way out of this dilemma is not to rely on a single memory component or technology, but to employ a memory hierarchy. A typical hierarchy is illustrated in Figure 4. As one goes down the hierarchy, the following occur:
Decreasing cost per bit
Increasing capacity
Increasing access time
Decreasing frequency of access of the memory by the processor
Thus, smaller, more expensive, faster memories are supplemented by larger, cheaper, slower memories.
Fig 4: The Memory Hierarchy
CACHE MEMORY PRINCIPLES
The concept of cache memory is illustrated in Figure 5a. There is a relatively large and slow main memory together with a smaller, faster cache memory. The cache contains a copy of portions of main memory. When the processor attempts to read a word of memory, a check is made to determine if the word is in the cache. If so, the word is delivered to the processor. If not, a block of main memory, consisting of some fixed number of words, is read into the cache and then the word is delivered to the processor. Because of the phenomenon of locality of reference, when a block of data is fetched into the cache to satisfy a single memory reference, it is likely that there will be future references to that same memory location or to other words in the block.
Fig 5: Cache and Main Memory
Figure 5b depicts the use of multiple levels of cache. The L2 cache is slower and typically larger than the L1 cache, and the L3 cache is slower and typically larger than the L2 cache.
Figure 6 depicts the structure of a cache/main-memory system. Main memory consists of up to 2n addressable words, with each word having a unique n-bit address. For mapping purposes, this memory is considered to consist of a number of fixed length blocks of K words each. That is, there are M = 2n/K blocks in main memory.
The cache consists of m blocks, called lines. Line is a basic unit of the cache, the term line is used, rather than the term block, for two reasons:
to avoid confusion with a main memory block, which contains the same number of data words as a cache line; and
because a cache line includes not only K words of data, just as a main memory block, but also include tag and control bits.
Fig 6: Cache/Main Memory Structure
Figure 7 illustrates the read operation. The processor generates the read address (RA) of a word to be read. If the word is contained in the cache, it is delivered to the processor. Otherwise, the block containing that word is loaded into the cache, and the word is delivered to the processor.
Fig 7: Cache Read operation
Fig 8: Typical Cache Organization
Elements of cache design
Although there are a large number of cache implementations, there are a few basic design elements that serve to classify and differentiate cache architectures. Table 2 lists key elements.
Table 2: Elements of cache Design
Cache Addresses
A logical cache, also known as a virtual cache, stores data using virtual addresses. The processor accesses the cache directly, without going through the MMU. A physical cache stores data using main memory physical addresses. Advantage of the logical cache is that cache access speed is faster than for a physical cache, because the cache can respond before the MMU performs an address translation. The disadvantage has to do with the fact that most virtual memory systems supply each application with the same virtual memory address space. That is, each application sees a virtual memory that starts at address 0. Thus, the same virtual address in two different applications refers to two different physical addresses. The cache memory must therefore be completely flushed with each application context switch, or extra bits must be added to each line of the cache to identify which virtual address space this address refers to.
Fig 9: Logical and Physical caches
Cache Size
There are several other motivations for minimizing cache size. The larger the cache, the larger the number of gates involved in addressing the cache. The result is that large caches tend to be slightly slower than small ones—even when built with the same integrated circuit technology and put in the same place on chip and circuit board.
Mapping Function
Because there are fewer cache lines than main memory blocks, an algorithm is needed for mapping main memory blocks into cache lines. Further, a means is needed for determining which main memory block currently occupies a cache line. The choice of the mapping function dictates how the cache is organized. Three techniques can be used: direct, associative, and set associative.
Direct mapping: The simplest technique, known as direct mapping, maps each block of main memory into only one possible cache line. The direct mapping technique is simple and inexpensive to implement. Its main disadvantage is that there is a fixed cache location for any given block. Thus, if a program happens to reference words repeatedly from two different blocks that map into the same line, then the blocks will be continually swapped in the cache, and the hit ratio will be low (a phenomenon known as thrashing).
Associative mapping: Associative mapping overcomes the disadvantage of direct mapping by permitting each main memory block to be loaded into any line of the cache. In this case, the cache control logic interprets a memory address simply as a Tag and a Word field. The Tag field uniquely identifies a block of main memory. To determine whether a block is in the cache, the cache control logic must simultaneously examine every line’s tag for a match. With associative mapping, there is flexibility as to which block to replace when a new block is read into the cache. The principal disadvantage of associative mapping is the complex circuitry required to examine the tags of all cache lines in parallel.
Set-associative mapping: Set-associative mapping is a compromise that exhibits the strengths of both the direct and associative approaches while reducing their disadvantages. In this case, the cache consists of a number sets, each of which consists of a number of lines. This is referred to as k-way set-associative mapping. With set-associative mapping, block Bj can be mapped into any of the lines of set j. As with associative mapping, each word maps into multiple cache lines. For set-associative mapping, each word maps into all the cache lines in a specific set, so that main memory block B0 maps into set 0, and so on.
Replacement Algorithms
Once the cache has been filled, when a new block is brought into the cache, one of the existing blocks must be replaced. For direct mapping, there is only one possible line for any particular block, and no choice is possible. For the associative and set associative techniques, a replacement algorithm is needed. To achieve high speed, such an algorithm must be implemented in hardware. A number of algorithms have been tried. There are four of the most common.
Least recently used (LRU): Replace that block in the set that has been in the cache longest with no reference to it. For two-way set associative, this is easily implemented.
First-in-first-out (FIFO): Replace that block in the set that has been in the cache longest. FIFO is easily implemented as a round-robin or circular buffer technique.
Least frequently used (LFU): Replace that block in the set that has experienced the fewest references.
A technique not based on usage (i.e., not LRU, LFU, FIFO, or some variant) is to pick a line at random from among the candidate lines.
Write Policy
Write through: All write operations are made to main memory as well as to the cache, ensuring that main memory is always valid. Any other processor–cache module can monitor traffic to main memory to maintain consistency within its own cache. The main disadvantage of this technique is that it generates substantial memory traffic and may create a bottleneck.
Write back: This minimizes memory writes. With write back, updates are made only in the cache. When an update occurs, a dirty bit, or use bit, associated with the line is set. Then, when a block is replaced, it is written back to main memory if and only if the dirty bit is set. The problem with write back is that portions of main memory are invalid, and hence accesses by I/O modules can be allowed only through the cache. This makes for complex circuitry and a potential bottleneck.
Line Size
When a block of data is retrieved and placed in the cache, not only the desired word but also some number of adjacent words are retrieved. As the block size increases from very small to larger sizes, the hit ratio will at first increase because of the principle of locality, which states that data in the vicinity of a referenced word are likely to be referenced in the near future. As the block size increases, more useful data are brought into the cache. The hit ratio will begin to decrease, however, as the block becomes even bigger and the probability of using the newly fetched information becomes less than the probability of reusing the information that has to be replaced.
Number of Caches
When caches were originally introduced, the typical system had a single cache. More recently, the use of multiple caches has become the norm. Two aspects of this design issue concern the number of levels of caches and the use of unified versus split caches.
SEMICONDUCTOR MAIN MEMORY
Organization
The basic element of a semiconductor memory is the memory cell. Although a variety of electronic technologies are used, all semiconductor memory cells share certain properties:
They exhibit two stable (or semistable) states, which can be used to represent binary 1 and 0.
They are capable of being written into (at least once), to set the state.
They are capable of being read to sense the state.
Table 3: Types of Memory
The most common type of memory is referred to as random-access memory (RAM). One distinguishing characteristic of RAM is that it is possible to read data from the memory and to write new data into the memory easily and rapidly. Both the reading and writing are accomplished through the use of electrical signals. The other distinguishing characteristic of RAM is that it is volatile. A RAM must be provided with a constant power supply. If the power is interrupted, then the data are lost. Thus, RAM can be used only as temporary storage. The two traditional forms of RAM used in computers are DRAM and SRAM.
A dynamic RAM (DRAM) is made with cells that store data as charge on capacitors. The presence or absence of charge in a capacitor is interpreted as a binary 1 or 0. Because capacitors have a natural tendency to discharge, dynamic RAMs require periodic charge refreshing to maintain data storage. The term dynamic refers to this tendency of the stored charge to leak away, even with power continuously applied. Although the DRAM cell is used to store a single bit (0 or 1), it is essentially an analog device. The capacitor can store any charge value within a range; a threshold value determines whether the charge is interpreted as 1 or 0.
In contrast, a static RAM (SRAM) is a digital device that uses the same logic elements used in the processor. In a SRAM, binary values are stored using traditional flip-flop logic-gate configurations. A static RAM will hold its data as long as power is supplied to it.
DRAM vs SRAM: Both static and dynamic RAMs are volatile; that is, power must be continuously supplied to the memory to preserve the bit values. A dynamic memory cell is simpler and smaller than a static memory cell. Thus, a DRAM is more dense (smaller cells more cells per unit area) and less expensive than a corresponding SRAM. On the other hand, a DRAM requires the supporting refresh circuitry. For larger memories, the fixed cost of the refresh circuitry is more than compensated for by the smaller variable cost of DRAM cells. Thus, DRAMs tend to be favored for large memory requirements. A final point is that SRAMs are generally somewhat faster than DRAMs. Because of these relative characteristics, SRAM is used for cache memory (both on and off chip), and DRAM is used for main memory.
ROM
A read-only memory (ROM) contains a permanent pattern of data that cannot be changed. A ROM is non-volatile; that is, no power source is required to maintain the bit values in memory. While it is possible to read a ROM, it is not possible to write new data into it. An important application of ROMs is microprogramming. The advantage of ROM is that the data or program is permanently in main memory and need never be loaded from a secondary storage device.
Programmable ROM
The PROM is non-volatile and may be written into only once. For the PROM, the writing process is performed electrically and may be performed by a supplier or customer at a time later than the original chip fabrication. Special equipment is required for the writing or “programming” process.
EPROM
Erasable programmable read-only memory (EPROM) is read and written electrically, as with PROM. However, before a write operation, all the storage cells must be erased to the same initial state by exposure of the packaged chip to ultraviolet radiation. Erasure is performed by shining an intense ultraviolet light through a window that is designed into the memory chip. This erasure process can be performed repeatedly; each erasure can take as much as 20 minutes to perform. Thus, the EPROM can be altered multiple times and, like the ROM and PROM, holds its data virtually indefinitely. For comparable amounts of storage, the EPROM is more expensive than PROM, but it has the advantage of the multiple update capability.
EEPROM
Electrically erasable programmable read-only memory (EEPROM) is a read-mostly memory that can be written into at any time without erasing prior contents; only the byte or bytes addressed are updated. The write operation takes considerably longer than the read operation, on the order of several hundred microseconds per byte. The EEPROM combines the advantage of non-volatility with the flexibility of being updatable in place, using ordinary bus control, address, and data lines. EEPROM is more expensive
than EPROM and also is less dense, supporting fewer bits per chip.
Flash memory
First introduced in the mid-1980s, flash memory is intermediate between EPROM and EEPROM in both cost and functionality. Like EEPROM, flash memory uses an electrical erasing technology. An entire flash memory can be erased in one or a few seconds, which is much faster than EPROM. In addition, it is possible to erase just blocks of memory rather than an entire chip. Flash memory gets its name because the microchip is organized so that a section of memory cells are erased in a single action or “flash.” However, flash memory does not provide byte-level erasure. Like EPROM, flash memory uses only one transistor per bit, and so achieves the high density (compared with EEPROM) of EPROM.
EXTERNAL MEMORY
Magnetic disk
A disk is a circular platter constructed of nonmagnetic material, called the substrate, coated with a magnetizable material. Traditionally, the substrate has been an aluminium or aluminum alloy material. More recently, glass substrates have been introduced. The glass substrate has a number of benefits, including the following:
Improvement in the uniformity of the magnetic film surface to increase disk reliability
A significant reduction in overall surface defects to help reduce read-write errors
Ability to support lower fly heights (described subsequently)
Better stiffness to reduce disk dynamics
Greater ability to withstand shock and damage
Data are recorded on and later retrieved from the disk via a conducting coil named the head; in many systems, there are two heads, a read head and a write head. During a read or write operation, the head is stationary while the platter rotates beneath it. The write mechanism exploits the fact that electricity flowing through a coil produces a magnetic field. Electric pulses are sent to the write head, and the resulting magnetic patterns are recorded on the surface below, with different patterns for positive and negative currents.
Redundant Array of Independent Disks (RAID)
The RAID scheme consists of seven levels, zero through six. These levels do not imply a hierarchical relationship but designate different design architectures that share three common characteristics:
RAID is a set of physical disk drives viewed by the operating system as a single logical drive.
Data are distributed across the physical drives of an array in a scheme known as striping, described subsequently.
Redundant disk capacity is used to store parity information, which guarantees data recoverability in case of a disk failure.
Table 4: RAID LEVELS
RAID Comparison
Table 5: Advantages and Disadvantages of RAID levels
Optical memory
In 1983, one of the most successful consumer products of all time was introduced: the compact disk (CD) digital audio system. The CD is a non-erasable disk that can store more than 60 minutes of audio information on one side. The huge commercial success of the CD enabled the development of low-cost optical-disk storage technology that has revolutionized computer data storage. A variety of optical-disk systems have been introduced.
Table 6: Optical disk products
Magnetic tape
Tape systems use the same reading and recording techniques as disk systems. The medium is flexible polyester tape coated with magnetizable material. The coating may consist of particles of pure metal in special binders or vapor-plated metal films. The tape and the tape drive are analogous to a home tape recorder system. Tape widths vary from 0.38 cm (0.15 inch) to 1.27 cm (0.5 inch). Tapes used to be packaged as open reels that have to be threaded through a second spindle for use.Today, virtually all tapes are housed in cartridges.
EXTERNAL DEVICES
We may wonder why one does not connect peripherals directly to the system bus. The reasons are as follows:
There are a wide variety of peripherals with various methods of operation. It would be impractical to incorporate the necessary logic within the processor to control a range of devices.
The data transfer rate of peripherals is often much slower than that of the memory or processor. Thus, it is impractical to use the high-speed system bus to communicate directly with a peripheral.
On the other hand, the data transfer rate of some peripherals is faster than that of the memory or processor. Again, the mismatch would lead to inefficiencies if not managed properly.
Peripherals often use different data formats and word lengths than the computer to which they are attached.
Thus, an I/O module is required, which has two major functions
Interface to the processor and memory via the system bus or central switch
Interface to one or more peripheral devices by tailored data links
Fig 10: Generic Model of an I/O module
An external device connected to an I/O module is often referred to as a peripheral device or, simply, a peripheral. We can broadly classify external devices into three categories:
Human readable: Suitable for communicating with the computer user. Examples of human-readable devices are video display terminals (VDTs) and printers.
Machine readable: Suitable for communicating with equipment. Examples of machine-readable devices are magnetic disk and tape systems, and sensors and actuators, such as are used in a robotics application.
Communication: Suitable for communicating with remote devices. Communication devices allow a computer to exchange data with a remote device, which may be a human-readable device, such as a terminal, a machine-readable device, or even another computer.
The interface to the I/O module is in the form of control, data, and status signals.
Control signals determine the function that the device will perform, such as send data to the I/O module (INPUT or READ), accept data from the I/O module (OUTPUT or WRITE), report status, or perform some control function particular to the device (e.g., position a disk head).
Data are in the form of a set of bits to be sent to or received from the I/O module.
Status signals indicate the state of the device. Examples are READY/NOT-READY to show whether the device is ready for data transfer.
Fig 11: Block Diagram of an External Device
Control logic associated with the device controls the device’s operation in response to direction from the I/O module.
The transducer converts data from electrical to other forms of energy during output and from other forms to electrical during input.
Keyboard/Monitor
The most common means of computer/user interaction is a keyboard/monitor arrangement. The user provides input through the keyboard. This input is then transmitted to the computer and may also be displayed on the monitor. In addition, the monitor displays data provided by the computer. The basic unit of exchange is the character. Associated with each character is a code, typically 7 or 8 bits in length. The most commonly used text code is the International Reference Alphabet (IRA). Each character in this code is represented by a unique 7-bit binary code; thus, 128 different characters can be represented. Characters are of two types: printable and control.
Printable characters are the alphabetic, numeric, and special characters that can be printed on paper or displayed on a screen.
Some of the control characters have to do with controlling the printing or displaying of characters; an example is carriage return. Other control characters are concerned with communications procedures.
For keyboard input, when the user depresses a key, this generates an electronic signal that is interpreted by the transducer in the keyboard and translated into the bit pattern of the corresponding IRA code. This bit pattern is then transmitted to the I/O module in the computer. At the computer, the text can be stored in the same IRA code.
For keyboard output, IRA code characters are transmitted to an external device from the I/O module. The transducer at the device interprets this code and sends the required electronic signals to the output device either to display the indicated character or perform the requested control function.
Disk Drive
A disk drive contains electronics for exchanging data, control, and status signals with an I/O module plus the electronics for controlling the disk read/write mechanism. In a fixed-head disk, the transducer is capable of converting between the magnetic patterns on the moving disk surface and bits in the device’s buffer. A moving-head disk must also be able to cause the disk arm to move radially in and out across the disk’s surface.
I/O MODULES
Module Function
The major functions or requirements for an I/O module fall into the following categories:
Control and timing: Coordinate the flow of traffic between internal resources and external devices. For example, the control of the transfer of data from an external device to the processor might involve the following sequence of steps:
i. The processor interrogates the I/O module to check the status of the attached device.
ii. The I/O module returns the device status.
iii. If the device is operational and ready to transmit, the processor requests the transfer of data, by means of a command to the I/O module.
iv. The I/O module obtains a unit of data (e.g., 8 or 16 bits) from the external device.
v. The data are transferred from the I/O module to the processor.
Processor communication: involves the following:
Command decoding: The I/O module accepts commands from the processor, typically sent as signals on the control bus. For example, an I/O module for a disk drive might accept the following commands: READ SECTOR, WRITE SECTOR, SEEK track number, and SCAN record ID. The latter two commands each include a parameter that is sent on the data bus.
Data: Data are exchanged between the processor and the I/O module over the data bus.
Status reporting: Because peripherals are so slow, it is important to know the status of the I/O module. For example, if an I/O module is asked to send data to the processor (read), it may not be ready to do so because it is still working on the previous I/O command. This fact can be reported with a status signal. Common status signals are BUSY and READY.
Address recognition: Just as each word of memory has an address, so does each I/O device. Thus, an I/O module must recognize one unique address for each peripheral it controls.
Device communication: This communication involves commands, status information, and data.
Data buffering: Data coming from main memory are sent to an I/O module in a rapid burst. The data are buffered in the I/O module and then sent to the peripheral device at its data rate. In the opposite direction, data are buffered so as not to tie up the memory in a slow transfer operation. Thus, the I/O module must be able to operate at both device and memory speeds. Similarly, if the I/O device operates at a rate higher than the memory access rate, then the I/O module performs the needed buffering operation.
Error detection: An I/O module is often responsible for error detection and for subsequently reporting errors to the processor. One class of errors includes mechanical and electrical malfunctions reported by the device (e.g., paper jam, bad disk track). Another class consists of unintentional changes to the bit pattern as it is transmitted from device to I/O module. Some form of error-detecting code is often used to detect transmission errors.
Fig 12: Block Diagram of an I/O Module
TECHNIQUES FOR I/O OPERATIONS
Three techniques are possible for I/O operations.
i. Programmed I/O
When the processor is executing a program and encounters an instruction relating to I/O, it executes that instruction by issuing a command to the appropriate I/O module. The I/O module will perform the requested action and then set the appropriate bits in the I/O status register. The I/O module takes no further action to alert the processor. In particular, it does not interrupt the processor. Thus, it is the responsibility of the processor periodically to check the status of the I/O module until it finds that the operation is complete.
To explain the programmed I/O technique, we view it first from the point of view of the I/O commands issued by the processor to the I/O module, and then from the point of view of the I/O instructions executed by the processor.
I/O Commands: To execute an I/O-related instruction, the processor issues an address, specifying
the particular I/O module and external device, and an I/O command. There are four types of I/O commands that an I/O module may receive when it is addressed by a processor:
Control: Used to activate a peripheral and tell it what to do. For example, a magnetic-tape unit may be instructed to rewind or to move forward one record.
Test: Used to test various status conditions associated with an I/O module and its peripherals. The processor will want to know that the peripheral of interest is powered on and available for use. It will also want to know if the most recent I/O operation is completed and if any errors occurred.
Read: Causes the I/O module to obtain an item of data from the peripheral and place it in an internal buffer. The processor can then obtain the data item by requesting that the I/O module place it on the data bus.
Write: Causes the I/O module to take an item of data (byte or word) from the data bus and subsequently transmit that data item to the peripheral.
I/O Instructions: With programmed I/O, there is a close correspondence between the I/O-related instructions that the processor fetches from memory and the I/O commands that the processor issues to an I/O module to execute the instructions. That is, the instructions are easily mapped into I/O commands, and there is often a simple one-to-one relationship. The form of the instruction depends on the way in which external devices are addressed.
ii. INTERRUPT-DRIVEN I/O
The problem with programmed I/O is that the processor has to wait a long time for the I/O module of concern to be ready for either reception or transmission of data. The processor, while waiting, must repeatedly interrogate the status of the I/O module. As a result, the level of the performance of the entire system is severely degraded.
An alternative is for the processor to issue an I/O command to a module and then go on to do some other useful work. The I/O module will then interrupt the processor to request service when it is ready to exchange data with the processor. The processor then executes the data transfer, as before, and then resumes its former processing.
iii. DIRECT MEMORY ACCESS
Interrupt-driven I/O, though more efficient than simple programmed I/O, still requires the active intervention of the processor to transfer data between memory and an I/O module, and any data transfer must traverse a path through the processor.
Thus, both these forms of I/O suffer from two inherent drawbacks:
i. The I/O transfer rate is limited by the speed with which the processor can test and service a device.
ii. The processor is tied up in managing an I/O transfer; a number of instructions must be executed for each I/O transfer.
There is somewhat of a trade-off between these two drawbacks. Consider the transfer of a block of data. Using simple programmed I/O, the processor is dedicated to the task of I/O and can move data at a rather high rate, at the cost of doing nothing else. Interrupt I/O frees up the processor to some extent at the expense of the I/O transfer rate. Nevertheless, both methods have an adverse impact on both processor activity and I/O transfer rate. When large volumes of data are to be moved, a more efficient technique is required: direct memory access (DMA).
DMA Function
DMA involves an additional module on the system bus. The DMA module is capable of mimicking the processor and, indeed, of taking over control of the system from the processor. It needs to do this to transfer data to and from memory over the system bus. For this purpose, the DMA module must use the bus only when the processor does not need it, or it must force the processor to suspend operation temporarily. The latter technique is more common and is referred to as cycle stealing, because the DMA module in effect steals a bus cycle.
When the processor wishes to read or write a block of data, it issues a command to the DMA module, by sending to the DMA module the following information:
Whether a read or write is requested, using the read or write control line between the processor and the DMA module.
The address of the I/O device involved, communicated on the data lines
The starting location in memory to read from or write to, communicated on the data lines and stored by the DMA module in its address register
The number of words to be read or written, again communicated via the data lines and stored in the data count register
The processor then continues with other work. It has delegated this I/O operation to the DMA module. The DMA module transfers the entire block of data, one word at a time, directly to or from memory, without going through the processor. When the transfer is complete, the DMA module sends an interrupt signal to the processor. Thus, the processor is involved only at the beginning and end of the transfer.
THE CENTRAL PROCESSING UNIT
Up to this point, we have viewed the processor essentially as a “black box” and have considered its interaction with I/O and memory. We now examine the internal structure and function of the processor. The processor consists of registers, the arithmetic and logic unit, the instruction execution unit, a control unit, and the interconnections among these components.
To understand the organization of the processor, let us consider the requirements placed on the processor, the things that it must do:
Fetch instruction: The processor reads an instruction from memory (register, cache, main memory).
Interpret instruction: The instruction is decoded to determine what action is required.
Fetch data: The execution of an instruction may require reading data from memory or an I/O module.
Process data: The execution of an instruction may require performing some arithmetic or logical operation on data.
Write data: The results of an execution may require writing data to memory or an I/O module.
To do these things, it should be clear that the processor needs to store some data temporarily. It must remember the location of the last instruction so that it can know where to get the next instruction. It needs to store instructions and data temporarily while an instruction is being executed. In other words, the processor needs a small internal memory.
Figure 13 is a simplified view of a processor, indicating its connection to the rest of the system via the system bus. The major components of the processor are an arithmetic and logic unit (ALU) and a control unit (CU). The ALU does the actual computation or processing of data. The control unit controls the movement of data and instructions into and out of the processor and controls the operation of the ALU. In addition, the figure shows a minimal internal memory, consisting of a set of storage locations, called registers.
Figure 14 is a slightly more detailed view of the processor. The data transfer and logic control paths are indicated, including an element labelled internal processor bus. This element is needed to transfer data between the various registers and the ALU because the ALU in fact operates only on data in the internal processor memory. The figure also shows typical basic elements of the ALU
Fig 13: The CPU with the system bus
Fig 14: Internal Structure of the CPU
Control Unit
The functional requirements for the control unit can be defined as those functions that the control unit must perform. The control unit causes operations to happen within the processor. The execution of a program consists of operations involving the processor elements. All micro-operations fall into one of the following categories:
Transfer data from one register to another.
Transfer data from a register to an external interface (e.g., system bus).
Transfer data from an external interface to a register.
Perform an arithmetic or logic operation, using registers for input and output.
The control unit performs two basic tasks:
Sequencing: The control unit causes the processor to step through a series of micro-operations in the proper sequence, based on the program being executed.
Execution: The control unit causes each micro-operation to be performed.
The key to how the control unit operates is the use of control signals. For the control unit to perform its function, it must have inputs that allow it to determine the state of the system and outputs that allow it to control the behavior of the system. These are the external specifications of the control unit.
Figure 15: General model of the control unit, showing all of its inputs and outputs.
The inputs are as follows:
Clock: This is how the control unit “keeps time.” The control unit causes one micro-operation (or a set of simultaneous micro-operations) to be performed for each clock pulse. This is sometimes referred to as the processor cycle time, or the clock cycle time.
Instruction register: The opcode and addressing mode of the current instruction are used to determine which micro-operations to perform during the execute cycle.
Flags: These are needed by the control unit to determine the status of the processor and the outcome of previous ALU operations.
Control signals from control bus: The control bus portion of the system bus provides signals to the control unit.
The outputs are as follows:
Control signals within the processor: These are two types: those that cause data to be moved from one register to another, and those that activate specific ALU functions.
Control signals to control bus: These are also of two types: control signals to memory, and control signals to the I/O modules.
Three types of control signals are used: those that activate an ALU function, those that activate a data path, and those that are signals on the external system bus or other external interface. All of these signals are ultimately applied directly as binary inputs to individual logic gates.
Let us consider again the fetch cycle to see how the control unit maintains control.
The control unit keeps track of where it is in the instruction cycle. At a given point, it knows that the fetch cycle is to be performed next. The first step is to transfer the contents of the PC to the MAR. The control unit does this by activating the control signal that opens the gates between the bits of the PC and the bits of the MAR. The next step is to read a word from memory into the MBR and increment the PC. The control unit does this by sending the following control signals simultaneously:
A control signal that opens gates, allowing the contents of the MAR onto the address bus
A memory read control signal on the control bus
A control signal that opens the gates, allowing the contents of the data bus to be stored in the MBR
Control signals to logic that add 1 to the contents of the PC and store the result back to the PC
Following this, the control unit sends a control signal that opens gates between the MBR and the IR.
This completes the fetch cycle except for one thing: The control unit must decide whether to perform an indirect cycle or an execute cycle next. To decide this, it examines the IR to see if an indirect memory reference is made.
The indirect and interrupt cycles work similarly. For the execute cycle, the control unit begins by examining the opcode and, on the basis of that, decides which sequence of micro-operations to perform for the execute cycle.
The Arithmetic and Logic Unit (ALU)
The ALU is that part of the computer that actually performs arithmetic and logical operations on data. All of the other elements of the computer system—control unit, registers, memory, I/O—are there mainly to bring data into the ALU for it to process and then to take the results back out.
Figure 16 indicates, in general terms, how the ALU is interconnected with the rest of the processor. Data are presented to the ALU in registers, and the results of an operation are stored in registers. These registers are temporary storage locations within the processor that are connected by signal paths to the ALU. The ALU may also set flags as the result of an operation. For example, an overflow flag is set to 1 if the result of a computation exceeds the length of the register into which it is to be stored. The flag values are also stored in registers within the processor. The control unit provides signals that control the operation of the ALU and the movement of the data into and out of the ALU.
Figure 16: ALU Inputs and Outputs
Register Organization
The registers in the processor perform two roles:
User-visible registers: Enable the machine- or assembly language programmer to minimize main memory references by optimizing use of registers.
Control and status registers: Used by the control unit to control the operation of the processor and by privileged, operating system programs to control the execution of programs.
User-Visible Registers
A user-visible register is one that may be referenced by means of the machine language that the processor executes. We can characterize these in the following categories:
General-purpose registers: This can be assigned to a variety of functions by the programmer. Sometimes their use within the instruction set is orthogonal to the operation. That is, any general-purpose register can contain the operand for any opcode. This provides true general-purpose register use. Often, however, there are restrictions. For example, there may be dedicated registers for floating-point and stack operations. In some cases, general-purpose registers can be used for addressing functions.
Data registers may be used only to hold data and cannot be employed in the calculation of an operand address.
Address registers may themselves be somewhat general purpose, or they may be devoted to a particular addressing mode. Examples include the following:
Segment pointers: In a machine with segmented addressing, a segment register holds the address of the base of the segment.
Index registers: These are used for indexed addressing and may be auto indexed.
Stack pointer: If there is user-visible stack addressing, then typically there is a dedicated register that points to the top of the stack. This allows implicit addressing; that is, push, pop, and other stack instructions need not contain an explicit stack operand.
Condition codes are partially visible to the user. Condition codes are bits set by the processor hardware as the result of operations. For example, an arithmetic operation may produce a positive, negative, zero, or overflow result. In addition to the result itself being stored in a register or memory, a condition code is also set. The code may subsequently be tested as part of a conditional branch operation.
Control and Status Registers
There are a variety of processor registers that are employed to control the operation of the processor. Most of these, on most machines, are not visible to the user. Some of them may be visible to machine instructions executed in a control or operating system mode.
Four registers are essential to instruction execution:
Program counter (PC): Contains the address of an instruction to be fetched
Instruction register (IR): Contains the instruction most recently fetched
Memory address register (MAR): Contains the address of a location in memory
Memory buffer register (MBR): Contains a word of data to be written to memory or the word most recently read
The four registers (PC, IR, MAR, MBR) are used for the movement of data between the processor and memory. Within the processor, data must be presented to the ALU for processing. The ALU may have direct access to the MBR and user-visible registers. Alternatively, there may be additional buffering registers at the boundary to the ALU; these registers serve as input and output registers for the ALU and exchange data with the MBR and user-visible registers.
Typically, the processor updates the PC after each instruction fetch so that the PC always points to the next instruction to be executed. A branch or skip instruction may also modify the contents of the PC. The fetched instruction is loaded into an IR, where the opcode and operand specifiers are analyzed. Data are exchanged with memory using the MAR and MBR. In a bus-organized system, the MAR connects directly to the address bus, and the MBR connects directly to the data bus. User-visible registers, in turn, exchange data with the MBR.
Pipelining Strategy
Instruction pipelining is the process of subdividing various stages of instruction such that it can be executed simultaneously, as new inputs are accepted at one end before previously accepted inputs appear as outputs at the other end.
As a simple approach, consider subdividing instruction processing into two stages: fetch instruction and execute instruction. There are times during the execution of an instruction when main memory is not being accessed. This time could be used to fetch the next instruction in parallel with the execution of the current one. Figure 15 depicts this approach. The pipeline has two independent stages. The first stage fetches an instruction and buffers it. When the second stage is free, the first stage passes it the buffered instruction. While the second stage is executing the instruction, the first stage takes advantage of any unused memory cycles to fetch and buffer the next instruction. This is also called instruction prefetch or fetch overlap. This approach, which involves instruction buffering, requires more registers. In general, pipelining requires registers to store data between stages.
Fig 17: 2-level Instruction Pipelining
To gain further speedup, the pipeline must have more stages. Let us consider the following decomposition of the instruction processing as illustrated in Figure 16.
Fetch instruction (FI): Read the next expected instruction into a buffer.
Decode instruction (DI): Determine the opcode and the operand specifiers.
Calculate operands (CO): Calculate the effective address of each source operand. This may involve displacement, register indirect, indirect, or other forms of address calculation.
Fetch operands (FO): Fetch each operand from memory. Operands in registers need not be fetched.
Execute instruction (EI): Perform the indicated operation and store the result, if any, in the specified destination operand location.
Write operand (WO): Store the result in memory.
Figure 18: 5-Level Instruction Pipelining
REDUCED INSTRUCTION SET ARCHITECTURE
Why CISC
Two principal reasons have motivated the CISC:
A desire to simplify compilers and
A desire to improve performance.
Both of these reasons was the shift to HLLs on the part of programmers; architects attempted to design machines that provided better support for HLLs.
However, complex machine instructions are often hard to exploit because the compiler must find those cases that exactly fit the construct. The task of optimizing the generated code to minimize code size, reduce instruction execution count, and enhance pipelining is much more difficult with a complex instruction set.
RISCs tend to emphasize register rather than memory references in CISCs, which require fewer bits. The following are common characteristics of RISC:
One instruction per cycle
Register-to-register operations
Simple addressing modes
Simple instruction formats
One machine instruction per machine cycle: A machine cycle is defined to be the time it takes to fetch two operands from registers, perform an ALU operation, and store the result in a register. With simple, one-cycle instructions, there is little or no need for microcode; the machine instructions can be hardwired. Such instructions should execute faster than comparable machine instructions on other machines, because it is not necessary to access a micro program control store during instruction execution.
Register to register: Most operations access memory with LOAD and STORE operations. This design feature simplifies the instruction set and therefore the control unit. For example, a RISC instruction set may include only one or two ADD instructions; the VAX has 25 different ADD instructions. Another benefit is that such an architecture encourages the optimization of register use, so that frequently
accessed operands remain in high-speed storage. This emphasis on register-to-register operations is notable for RISC designs. Contemporary CISC machines provide such instructions but also include memory to memory and mixed register/memory operations.
Simple addressing modes: Almost all RISC instructions use simple register addressing. Several additional modes, such as dis placement and PC-relative, may be included. Other, more complex modes can be synthesized in software from the simple ones. Again, this design feature simplifies the instruction set and the control unit.
Simple instruction formats: Generally, only one or a few formats are used. Instruction length is fixed and aligned on word boundaries. Field locations, especially the opcode, are fixed. This design feature has a number of benefits. With fixed fields, opcode decoding and register operand accessing can occur simultaneously. Simplified formats simplify the control unit. Instruction fetching is optimized because word-length units are fetched. Alignment on a word boundary also means that a single instruction does not cross page boundaries.
CISC versus RISC Characteristics
After the initial enthusiasm for RISC machines, there has been a growing realization that:
RISC designs may benefit from the inclusion of some CISC features
CISC designs may benefit from the inclusion of some RISC features.
The result is that the more recent RISC designs, notably the PowerPC, are no longer “pure” RISC and the more recent CISC designs, notably the Pentium II and later Pentium models, do incorporate some RISC characteristics.
For purposes of this comparison, the following are considered typical of a classic RISC:
1. A single instruction size.
2. That size is typically 4 bytes.
3. A small number of data addressing modes, typically less than five.
4. No indirect addressing that requires you to make one memory access to get the address of another operand in memory.
5. No operations that combine load/store with arithmetic (e.g., add from memory, add to memory).
6. No more than one memory-addressed operand per instruction.
7. Does not support arbitrary alignment of data for load/store operations.
8. Maximum number of uses of the memory management unit (MMU) for a data address in an instruction.
9. Number of bits for integer register specifier equal to five or more. This means that at least 32 integer registers can be explicitly referenced at a time.
10. Number of bits for floating-point register specifier equal to four or more. This means that at least 16 floating-point registers can be explicitly referenced at a time.
SPARC
SPARC (Scalable Processor Architecture) refers to an architecture defined by Sun Microsystems. Sun developed its own SPARC implementation but also licenses the architecture to other vendors to produce SPARC-compatible machines. The SPARC architecture is inspired by the Berkeley RISC I machine, and its instruction set and register organization is based closely on the Berkeley RISC model.
As with the Berkeley RISC, the SPARC makes use of register windows. Each window consists of 24 registers, and the total number of windows is implementation dependent and ranges from 2 to 32 windows. Physical registers 0 through 7 are global registers shared by all procedures. Each process sees logical registers 0 through 31. Logical registers 24 through 31, referred to as ins, are shared with the calling (parent) procedure; and logical registers 8 through 15, referred to as outs, are shared with any called (child) procedure. These two portions overlap with other windows. Logical registers 16 through 23, referred to as locals, are not shared and do not overlap with other windows. Again, the availability of 8 registers for parameter passing should be adequate in most cases.
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